1. Field of the Invention
The present invention generally relates to a cell of mask read only memory (ROM), and particularly relates to a cells array of mask ROM with both low word line resistance and larger process window.
2. Description of the Prior Art
Essential configuration of cells array of conventional mask ROM is shown in FIG. 1 which is a top-view illustration. Numerous word lines 11 crisscross numerous bit lines 12, each word line 11 is essentially parallel to and insulated to other word lines 11, and each bit line 12 is essentially parallel to and insulated to other bit lines 12. Moreover, one cell 13 of mask ROM is formed by gate, where one word line 11 crosses one bit line 12, and surrounding space. In general, as shown in FIG. 2A which is cross-sectional illustration along AA1, structure of conventional cell 13 comprises doped regions 22, and gate 23. Doped regions 22 are located in substrate 21 and are used to form sources and drains, gate 23 at least includes gate dielectric and gate conductor (not shown in FIG. 2A).
Significantly, whether any cell 13 is opened or closed is decided by how threshold voltage of this cell 13 is adjusted in a code process. Further, in the code process, photoresist is used to cover part of cells which need not to adjust threshold voltage but to expose other part of cells which need to adjust threshold voltage in accordance with data to be stored, and then an ion implantation process is performed to implant numerous ions into part of substrate which under gates should be adjusted corresponding threshold voltage. However, owing to limitation of structure of cells 13 (or cells array), some defects of code process will is more serious while scale of mask ROM is continually decreased: because photoresist 24 is used by this code process to control which cells are exposed and then ions 25 can be implanted into these uncovered cells, as FIG. 2B shows, defects will be happened while location of photoresist 24 is misalined, as FIG. 2C shows, that will let part of ions 25 are implanted into cells that should be not be implanted. Reasonably, because that distance between neighboring gates is decreased as size of cells is decreased, acceptable misalignment of photoresist also is proportionally decreased. In other words, process window is decreased and then both cost of corresponding fabrication is increased and quality of corresponding products is decreased.
Furthermore, because that lateral scatter of ions in the ions implantation process always is negligible, no matter it is owing to laterally incident ions 25, owing to scatters of ions induced by gate 23, or is owing to other unavoidable limitations of practical fabrication. It is indisputable that interference between neighboring cells always is negligible, except while scale of mask ROM cells is continually decreased.
Besides, because sources and drains of conventional mask ROM cells is provided by doped regions 22 which located in substrate 21, it also is significantly that thickness of doped regions 22 is decreased as scale of cells is decreased, and then an unavoidable defect is that resistance of doped regions 22 is increased.
Accordingly, conventional structure of cells of mask ROM can not avoid some defects that are more and more serious while scale of cells is continually decreased. Thus, it is desired to develop a new mask ROM cell and a new mask ROM cells array to let mask ROM can be properly applied in the deep-submicron devices.
The primary object of the invention is to present cell of mask ROM, and especially is to present suitable cell of mask ROM for deep submicron product.
Another object of the invention is to provide a cells array of mask ROM with low word line resistance and larger process window.
One preferred embodiment is a cells array of mask read only memory, at least includes numerous essentially parallel cells chains and numerous isolation dielectric layers which are located between any two adjacent cells chains. Each cells chain at least includes: numerous gates, numerous doped regions, numerous polysilicon layers, numerous cover dielectric layers, a conductor layer and numerous isolation dielectric layers. Moreover, each gate at least include a gate dielectric layer, a gate conductor layer and a spacer, and height of spacer is larger than summation of thickness of gate dielectric layer and thickness of gate conductor layer; doped regions are located in the substrate, and each doped region is located between two neighboring gates; each doped region is covered by one polysilicon layer, and height of each polysilicon layer is larger than summation of thickness of gate dielectric layer and thickness of each gate conductor layer; each polysilicon layer is covered by one cover dielectric layer; and conductor layer covers both the gates and the cover dielectric layers. Moreover, height of each isolation dielectric layer is larger than summation of thickness of gate dielectric layer and thickness of any gate conductor layer.